(1) Field of the Invention
The present invention relates generally to semiconductor integrated circuit technology and more particularly to split gate memory cells used in flash EPROMs (Electrically Erasable Programmable Read Only Memory).
(2) Description of Prior Art
Increased performance in computers is often directly related to a higher level of circuit integration. Tolerances play an important role in the ability to shrink dimensions on a chip. Self-alignment of components in a device serves to reduce tolerances and thus improve the packing density of chips. Other techniques can be important in shrinking device size. A method is disclosed later in the embodiments of the present invention of forming a structure with self-aligned bit line contact to word line through which a significant reduction in the area of the split gate flash cell is possible.
As is well known in the art, split gate flash cells have bit lines and word lines and bit contacts that connect bit lines to drain regions. Bit lines and bit contacts are insulated from the word lines by an interlevel dielectric layer. The separation between bit contacts and word lines must be maintained large enough so as to avoid possible shorts that could develop between adjacent bit contacts and word lines. Bit contact to word line separations are determined by the positions of bit contact openings, which are set by a design rule. In arriving at the design rule the possibility of misalignment must be taken into account, which results in a required separation well beyond that needed to avoid development of shorts. This requirement for increased separation, arising from the need to account for unavoidable misalignment, limits the ability to decrease cell size. Self-alignment of the bit contact to the word line, as in the structures disclosed by the present invention, eliminates the reliability issue, allows a reduction in cell area and facilitates shrinking the cell size.
A traditional method of fabricating a split gate flash memory cell is presented in FIGS. 1a–1g, where top views of the cell are presented at successive stages of the process and in FIGS. 2a–2g, which show the corresponding cross-sections. A floating gate oxide, 6, is formed on a semiconductor substrate, 2, which preferably is a silicon substrate, to a thickness of about 80 Angstroms, followed by deposition of a poly 1 layer, 8, to a depth of about 800 Angstroms. Active regions, 10, are defined using isolating regions, such as shallow trench isolation regions, 4. This is followed by deposition of a nitride layer, which preferably is a silicon nitride layer to a depth of about 2500 Angstroms. A photoresist layer, 14, is then formed as shown in FIGS. 1b and 2b. The photoresist pattern, 14, is used in etching the silicon nitride layer to achieve the shape of region 12 of FIG. 2b. It is advantages to perform a poly 1 etch so as to achieve the shape of region 8 as shown in FIG. 2b. Details of the method to fabricate such sharp poly tips are presented in U.S. Pat. No. 6,090,668 to Lin et al., which is herein incorporated by reference. Such sharp poly tips are advantageous because they provide enhanced erase speed. After removal of the photoresist, an oxide 2 layer, 16, is deposited to a thickness of about 3000 Angstroms and a CMP (chemical-mechanical polishing) step is performed. A second photoresist layer, 18, is formed and used in successively etching the silicon nitride layer and the poly 1 layer to achieve the structure shown in FIGS. 1c and 2c. Source regions 20 are formed by a P ion implantation at energy of about 20 keV and to a dose of about 4E14 per cm2. Removal of the second photoresist layer is followed by deposition of an oxide 3 layer to a depth of about 500 Angstroms, which enhances the lateral diffusion of the source implant. An oxide 3 etching step is performed to achieve oxide 3 spacers, 22. A polysilicon deposition is performed to a depth of about 3000 Angstroms and a CPM step on this layer produces a poly 2 region 24, which serves to contact the source 20. At this stage the structure is as depicted in FIGS. 1d and 2d. The traditional method proceeds with oxidation of poly 2, 24, to form about 200 Angstroms of oxide 4, 26. Next the nitride layer 12 is removed, and successive etches are performed of the poly 1 layer, 8, and floating gate oxide 1 layer, 6. After a poly 3 deposition, 30, to about 2000 Angstroms, the structure is as shown in FIGS. 1e and 2e. Etching the poly 3 layer, poly spacers, 30, are formed that serve as word lines. A drain implant is now performed that usually is an As implant at energy about 60 keV and to a dose of about 4E15 per cm2. This forms the drain regions 36. An interlevel dielectric (ILD) layer, 38 is deposited. A photoresist layer is formed and patterned so that upon etching of the IDL layer, contacts are opened to the drain regions. A metal 1 deposition follows removal of the photoresist layer. Another photoresist layer is formed and patterned so that after etching metal 1 bit lines 34 are formed connecting to the drain regions, 36 through the metal 1 contact regions 32. This completes the formation of a traditional split gate flash cell, which is shown in FIGS. 1g and 2g. 
Bit lines, 34 and bit contacts, 32 are insulated from the word lines, 30 by an interlevel dielectric layer, 38. The minimum separation, 40, is between bit contacts and word lines and this separation must be maintained large enough so as to avoid possible shorts that could develop between adjacent bit contacts and word lines. Bit contact to word line separations are determined by the positions of bit contact openings relative to word lines and the dimensions of the openings, which are set by design rules. In arriving at the design rule the possibility of misalignment and variability in the production of contact openings must be taken into account, which results in a required minimum separation well beyond that needed to avoid development of shorts. This requirement for increased separation limits the ability to decrease cell size. Self-alignment of the bit contact to the word line, as in the structures disclosed by the present invention, eliminates the reliability issue, allows a reduction in cell area and facilitates slinking the cell size.
A split-gate flash memory cell having self-aligned source and floating gate self aligned to control gate, is disclosed in U.S. Pat. No. 6,228,695 to Hsieh et al. In U.S. Pat. No. 6,211,012 to Lee et al. there is disclosed an ETOX flash memory cell utilizing self aligned processes for forming source lines and landing pads to drain regions. In U.S. Pat. No. 5,679,591 to Lin et al. there is disclosed a raised-bitline contactless flash memory cell. A method for fabricating a split-gate EPROM cell utilizing stacked etch techniques is provided in U.S. Pat. No. 5,091,327 to Bergemont.